In integrated circuits, a great number of devices and circuits are fabricated on a single chip. Various kinds of devices like transistors, resistors, and capacitors are formed together. Each device must operate independently without interfering with each other, especially under the higher and higher packing density of the integrated circuits. An isolation region is formed on the semiconductor substrate for separating different devices or different functional regions. The isolation region is generally a non-active and insulated region for isolating between devices, wells, and functional regions.
LOCOS (local oxidation of silicon) is a widely applied technology in forming the isolation region. The isolation regions are created by oxidizing the portion of the silicon substrate between each active devices and functional regions. The LOCOS technology provide the isolation region with a simple manufacturing process and low cost, especially when compared with other trench isolation processes. However, with the fabrication of semiconductor integrated circuits becomeing densely packed, the application of the LOCOS technology is quite limited. For highly packed circuits like the circuits with devices of deep sub-micrometer feature sizes, the LOCOS process has several challenges in fulfilling the isolating and packing density specifications.
The trench isolation process, or the shallow trench isolation (STI) process, is another isolation process proposed especially for semiconductor chips with high packing density. A trench region is formed in the semiconductor with a depth deep enough for isolating the devices or different wells. In general, a trench is etched and refilled with insulating materials by the trench isolation formation process. The refilled trench regions are employed for the application in the VLSI and ULSI level. In addition, capacitors can also be formed within the trench by filling both insulating and conductive materials sequentially for the application of forming memory cells.
Shallow trench isolation has emerged as the solution for deep sub-micron transistor isolation due to its scalability, planar topography and potentially low thermal budget. In U.S. Pat. No. 5,443,794 to Fazan et al., a method for using spacers to form isolation trenches with improved corners is proposed. They mention that the limits of the standard LOCOS process have motivated the search for and the development of new isolation schemes. The trench isolation is a promising candidate as it uses a fully recessed oxide, has no bird's beak, is fully planar, and does not suffer from the field oxide thinning effect. A smooth trench profile with a self-aligned cap or dome is created in their invention.
For providing better insulating characteristics, a deep trench isolation scheme has been reported. The deep trench isolation increases the packing density and improve the latch-up immunity in CMOS (complementary metal oxide semiconductor)/bipolar devices. R. Bashir and F. Hebert disclosed a planarized trench isolation and field oxide formation using poly-silicon (PLATOP) in their work: "PLATOP: A Novel Planarized Trench Isolation and Field Oxide Formation Using Poly-Silicon" (IEEE Electron Device Letters, vol. 17, no. 7, 1996). It is disclosed that a process highly applicable to high density and high performance CMOS/bipolar processes is needed. The process should not suffer from the conventional limitations of LOCOS-based isolation. The deep trench isolation is finding abundant use in semiconductor processes to increase packing density and latch-up immunity. The difficulties reported include lateral encroachment by bird's beak, formation of thick oxide, combination of deep trench and field isolation, and area and loading effects of planarization process.
In U.S. Pat. No. 5,474,953 to Shimizu et al., a method is reported for forming an isolation region comprising a trench isolation region and a selective oxidation film involved in a semiconductor device. A semiconductor device including both emitter coupled logic circuits (ECL circuits) involving super high speed performance bipolar transistors and super high integrated CMOS circuits with a low power consumption has been developed and known in the art. Both the CMOS and the bipolar devices are formed on a single chip. Thus, isolation structures fulfilling the needs of the various devices and circuits is highly demanded for providing designed functionality of the circuits.